1. Field of Invention
This invention relates to a semiconductor device and the operation thereof, and more particularly to a vertical capacitor-less dynamic random access memory (DRAM) cell, a DRAM array based on the cells, and a method of operating the DRAM cell.
2. Description of Related Art
A traditional DRAM cell includes an access transistor and a capacitor coupled thereto, therefore suffering from a complicated fabricating process and taking a larger lateral area that limits the integration degree and the data storage volume. For these issues, capacitor-less DRAM has been provided.
Capacitor-less DRAM cells store data by floating body effect, and are classified into planar and vertical types. A planar capacitor-less DRAM cell includes a planar MOS transistor on a SOI substrate, and a vertical capacitor-less DRAM cell includes a vertical MOS transistor including stacked source, active and drain layers. Both types of cells are written by gate-induced drain leakage (GIDL) or impact ionization and thus have a gate overlapping the source/drain (S/D) and a heavier S/D junction, so that the requirement to gate dielectric quality is high and the junction leakage is high due to the S/D-gate overlap. Moreover, the planar capacitor-less DRAM cell further suffers from a large lateral area, and the vertical capacitor-less DRAM cell further suffers from high power consumption in the impact ionization writing mechanism.